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LG Semicon Co.,Ltd.
Description
The GM71C(S)4400C/CL is the new generation dynamic RAM organized 1,048,576 words x 4 bit. GM71C(S)4400C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)4400C/CL offers Fast Page Mode as a high speed access Mode. Multiplexed address inputs permit the GM71C(S)4400C/CL to be packaged in a standard 300mil 20(26) pin plastic SOJ and standard 300mil 20(26) pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V+/-10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL.
GM71C(S)4400C/CL
1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
Features
* 1,048,576 Words x 4 Bit Organization * Fast Page Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time (Unit: ns)
tRAC
GM71C(S)4400C/CL-60 GM71C(S)4400C/CL-70 GM71C(S)4400C/CL-80 60 70 80
tCAC
15 20 20
tRC
110 130 150
tPC
40 45 50
Pin Configuration 20 (26) SOJ
I/O1 I/O2 WE RAS A9 VSS I/O4 I/O3 CAS OE I/O1 I/O2 WE RAS A9
1 2 3 4 5
* Low Power Active : 605/550/495mW (MAX) Standby : 5.5mW (CMOS level : MAX) 1.1mW (L-version) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 1024 Refresh Cycles/16ms * 1024 Refresh Cycles/128ms (L-version) * Battery Back Up Operation (L-version)
20 (26) TSOP II
20 19 18 17 16
VSS I/O4 I/O3 CAS OE
VSS I/O4 I/O3 CAS OE
20 19 18 17 16
1 2 3 4 5
I/O1 I/O2 WE RAS A9
A0 A1 A2 A3 VCC
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
A0 A1 A2 A3 VCC
6 7 8 9 10
15 14 13 12 11
A8 A7 A6 A5 A4
A8 A7 A6 A5 A4
15 14 13 12 11
6 7 8 9 10
A0 A1 A2 A3 VCC
NORMAL TYPE
REVERSE TYPE
(Top View)
(Top View)
1
LG Semicon
GM71C(S)4400C/CL
Function
Address Inputs Refresh Address Inputs Data Input / Data Output Row Address Strobe Column Address Strobe
Pin Description
Pin
A0-A9 A0-A9 I/O1-I/O4 RAS CAS
Pin
WE OE VCC VSS
Function
Read/Write Enable Output Enable Power (+5V) Ground
Ordering Information
Type No.
GM71C(S)4400CJ/CLJ-60 GM71C(S)4400CJ/CLJ-70 GM71C(S)4400CJ/CLJ-80 GM71C(S)4400CT/CLT-60 GM71C(S)4400CT/CLT-70 GM71C(S)4400CT/CLT-80 GM71C(S)4400CR/CLR-60 GM71C(S)4400CR/CLR-70 GM71C(S)4400CR/CLR-80
Access Time
60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns
Package
300 Mil, 20 (26) Pin Plastic SOJ 300 Mil, 20 (26) Pin Plastic TSOP II (Normal Type) 300 Mil, 20 (26) Pin Plastic TSOP II (Reverse Type)
Absolute Maximum Ratings*
Symbol TA TSTG VIN/VOUT VCC IOUT PD Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage on any Pin Relative to VSS Voltage on VCC Relative to VSS Short Circuit Output Current Power Dissipation
Rating
0 ~ 70 -55 ~ 125 -1.0 ~ 7.0 -1.0 ~ 7.0 50 1.0
Unit
C C V V mA W
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol VCC VIH VIL VIL Parameter
Supply Voltage Input High Voltage Input Low Voltage (I/O Pin) Input Low Voltage (Others)
Min
4.5 2.4 -1.0 -2.0
Typ
5.0 -
Max
5.5 6.5 0.8 0.8
Unit
V V V V
2
LG Semicon
GM71C(S)4400C/CL
DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)
Symbol VOH VOL ICC1 Parameter
Output Level Output "H" Level Voltage (IOUT = -5mA) Output Level Output "L" Level Voltage (IOUT = 4.2mA) Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS= VIH, DOUT = High-Z) RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (RAS Cycling, CAS = VIH, tRC = tRC min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (RAS = VIL, CAS, Address Cycling: tPC = tPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >= VCC - 0.2V , DOUT=High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns
Min Max Unit Note
2.4 0 60ns 70ns 80ns VCC 0.4 110 100 90 2 110 100 90 110 100 90 1 200 110 100 90 300 uA 4, 5 mA mA uA 5 4, 5 mA 1, 3 mA 2 mA mA 1, 2 V V
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
Battery Back Up Current (Standby with CBR Refresh) (tRC=125us, tRAS<=1us, WE=VIH, CAS=VIL, OE, Address and DIN=VIH or VIL, DOUT=High-Z) Standby Current RAS = VIH CAS = VIL DOUT = Enable Input Leakage Current Any Input (0V<=VIN<=7V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<=7V)
ICC8
-10 -10
5 10 10
mA uA uA
1
II(L) IO(L)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. L-version. 5. VCC-0.2V<=VIH<=6.5V, 0V<=VIL<=0.2V.
3
LG Semicon
GM71C(S)4400C/CL
Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Data Input, Output Capacitance (Data-In, Out)
Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol CI1 CI2 CI/O Min
-
Max
5 7 10
Unit
U U U
Note
1 1 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16)
Test Conditions Input rise and fall times: 5ns Output load : 2 TTL gate + CL (100U) Input, output timing reference levels: 0.8V, 2.4V (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read or Write Cycle Time RAS Precharge Time RAS Pulse Width CAS Pulse Width Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time RAS Hold Time CAS Hold Time CAS to RAS Precharge Time OE to DIN Delay Time OE Delay Time from DIN CAS Set-up Time from DIN Transition Time (Rise and Fall) Refresh Period Refresh Period (L-version) GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
Note
Min Max Min Max Min Max 110 40 60 15 0 10 0 15 20 15 15 60 10 15 0 0 3 10,000 10,000
tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT tREF
130 50 70 20 0 10 0 15 20 15 20 70 10 20 0 0 3 -
10,000 10,000
150 60 80 20 0 10 0 15 20 15 20 80 10 20 0 0 3 -
10,000 10,000
45 30 50 16 128
50 35 50 16 128
60 40 50 16 128
8 9
7
4
LG Semicon
GM71C(S)4400C/CL
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Read Cycle
Symbol Parameter
Access Time from RAS Access Time from CAS Access Time from Address Access Time from OE Read Command Setup Time Read Command Hold Time to CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Output Buffer Turn-off Time Output Buffer Turn-off Time from OE CAS to DIN Delay Time OE Pulse width
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Note
2,3,17
3, 4, 13, 17 3, 5, 13, 17
Min Max Min Max Min Max 0 0 0 30 0 0 15 15 60 15 30 15 15 15 0 0 0 35 0 0 20 20 70 20 35 20 15 15 0 0 0 40 0 0 20 20 80 20 40 20 15 15 -
tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tOFF1 tOFF2 tCDD tOEP
3,17
18 18
6 6
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Min Max Min Max Min Max 0 15 10 15 15 0 15 0 15 10 20 20 0 15 0 15 10 20 20 0 15 -
Unit
ns ns ns ns ns ns ns
Note
10
tWCS tWCH
tWP
tRWL tCWL tDS tDH
11 11
5
LG Semicon
GM71C(S)4400C/CL
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time OE Hold Time from WE
Unit
ns ns ns ns ns
Note
Min Max Min Max Min Max 150 80 35 50 15 180 95 45 60 20 200 105 45 65 20 -
tRWC tRWD tCWD tAWD tOEH
10 10 10
Refresh Cycle
Symbol Parameter
CAS Set-up Time (CAS-before-RAS Refresh Cycle) CAS Hold Time (CAS-before-RAS Refresh Cycle) RAS Precharge to CAS Hold Time CAS Precharge Time in Normal Mode
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Min Max Min Max Min Max 10 10 10 10 10 10 10 10 10 10 10 10 -
Unit
Note
tCSR tCHR tRPC tCPN
ns ns ns ns
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode CAS Precharge Time Fast Page Mode RAS Pulse Width Access Time from CAS Precharge RAS Hold Time from CAS Precharge Fast Page Mode Read-Modify-Write Cycle CAS Precharge to WE Delay Time Fast Page Mode Read-Modify-Write Cycle Time
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
ns ns ns ns ns ns
Note
Min Max Min Max Min Max 40 10 35 55 100,000
tPC tCP tRASP tACP tRHCP tCPW tPRWC
45 10 40 65
100,000
50 10 45 70
100,000
12
3,13,17
35 -
40 -
45 -
80
-
95
-
100
-
ns
10
6
LG Semicon
GM71C(S)4400C/CL
Test Mode Cycle
Symbol Parameter
Test Mode WE Setup Time Test Mode WE Hold Time
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
ns ns
Note
Min Max Min Max Min Max 0 10 0 10 0 10 -
tWS tWH
Counter Test Cycle
Symbol Parameter
CAS Precharge Time in Counter Test Cycle
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
Min Max Min Max Min Max 40 40 40 ns
tCPT
Notes: 1. AC Measurements assume tT = 5ns. 2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2TTL loads and 100U. 4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max). 5. Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max). 6. tOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 7
LG Semicon
GM71C(S)4400C/CL
10. tWCS, tRWD, tCWD tCPW and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in delayed write or a read modify write cycle. 12. tRASP defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of tAA or tCAC or tACP. 14. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is low level. In order to end this test mode operation, perform a RAS only refresh cycle or a CAS-before-RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
8
LG Semicon
GM71C(S)4400C/CL
Unit: Inches (mm)
Package Dimension
20 (26) SOJ
0.025(0.63) MIN 0.039(1.00) MAX 0.305(7.75) MAX 0.340(8.64) MAX
0.260(6.60) MIN
0.275(6.99) MAX 0.008(0.20)
0.295(7.49) MIN
0.330(8.38) MIN
0.661(16.80) MIN 0.669(17.00) MAX
0.085(2.16) MIN 0.103(2.61) MAX
0.128(3.25) MIN 0.148(3.76) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.021(0. 53) MAX 0.026(0.66) MIN 0.036(0.91) MAX
20 (26) TSOP II
0~8 0.308(7.82) MAX 0.292(7.42) MIN
o
0.012(0.30) MIN 0.028(0.70) MAX
0.009(0.22) MAX 0.667(16.94) MIN 0.690(17.54) MAX 0.041(1.03) MIN 0.048(1.23) MAX 0.012(0.30) MIN 0.020(0.50) MAX 0.050(1.27) TYP 0.001(0.03) MIN 0.009(0.23) MAX
0.371(9.42) MAX
0.355(9.02) MIN
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